Self-aligned body tie for a partially depleted SOI device...

Details Self-aligned body tie for a partially depleted SOI device... Self-aligned body tie for a partially depleted SOI device...

2007-03-20

2007-03-20

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S195000, C438S157000, C438S223000, C438S224000, C257SE27112, C257SE21545

Reexamination Certificate

active

11096014

ABSTRACT:
A silicon-on-insulator (SOI) device structure100formed using a self-aligned body tie (SABT) process. The SABT process connects the silicon body of a partially depleted (PD) structure to a bias terminal. In addition, the SABT process creates a self-aligned area of silicon around the edge of the active areas, as defined by the standard transistor active area mask, providing an area efficient device layout. By reducing the overall gate area, the speed and yield of the device may be increased. In addition, the process flow minimizes the sensitivity of critical device parameters due to misalignment and critical dimension control. The SABT process also suppresses the parasitic gate capacitance created with standard body tie techniques.

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