Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-09-18
2007-09-18
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S154000
Reexamination Certificate
active
10426084
ABSTRACT:
According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for improving the accuracy of information available to a cache coherence controller are provided in order to allow the cache coherence controller to reduce the number of transactions in a multiple cluster system. Cache state information is provided to a home cluster cache coherence controller to allow silent evictions of shared memory lines and change to dirty associated intervening requests to be efficiently handled.
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Kim et al., “Power-aware Partitioned Cache Architectures”, © 2001 ACM, pp. 64-67.
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HyperTransport ™ I/O Link Specification Revision 1.03,HyperTransport™ Consortium, Oct. 10, 2001, Copyright© 2001 HyperTransport Technology Consortium.
Beyer & Weaver, LLP
Newisys Inc.
Peugh Brian R.
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