Memory device having at least a first and a second operating...

Details Memory device having at least a first and a second operating... Memory device having at least a first and a second operating...

2007-04-24

2007-04-24

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000

Reexamination Certificate

active

11153679

ABSTRACT:
An integrated circuit memory device comprises a latch circuit to load an address using a first control signal. A first signal level transition of the first control signal is used to load the address. A memory array stores data at a memory location that is based on the address. An output buffer outputs the data after a period of time from the first signal level transition. A register stores a value that specifies between at least a first mode and a second mode. When the value specifies the first mode, the output buffer outputs the data in response to address transitions that occur after the first signal level transition. When the value specifies the second mode, the output buffer outputs data synchronously with respect to an external clock signal.

REFERENCES:
patent: 5594704 (1997-01-01), Konishi et al.
patent: 6026465 (2000-02-01), Mills et al.
patent: 6791898 (2004-09-01), Manapat et al.
patent: 2004/0153602 (2004-08-01), Lovett
patent: 2005/0169091 (2005-08-01), Miki et al.

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