Integrated semiconduct memory with test circuit

Details Integrated semiconduct memory with test circuit Integrated semiconduct memory with test circuit

2007-09-04

2007-09-04

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S189110

Reexamination Certificate

active

11235540

ABSTRACT:
An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.

REFERENCES:
patent: 2003/0223277 (2003-12-01), Origasa
patent: 1252631 (2001-10-01), None

Affiliated with

Also associated with

Rating

Integrated semiconduct memory with test circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated semiconduct memory with test circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated semiconduct memory with test circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3761183