Semiconductor device having NMOSFET and PMOSFET and...

Details Semiconductor device having NMOSFET and PMOSFET and... Semiconductor device having NMOSFET and PMOSFET and...

2007-09-04

2007-09-04

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S371000, C257S369000, C257S377000, C257S412000

Reexamination Certificate

active

11016923

ABSTRACT:
An element isolation dielectric film is formed around device regions in a silicon substrate. The device regions are an n-type diffusion region, a p-type diffusion region, a p-type extension region, an n-type extension region, a p-type source/drain region, an n-type source/drain region, and a nickel silicide film. Each gate dielectric film includes a silicon oxide film and a hafnium silicate nitride film. The n-type gate electrode includes an n-type silicon film and a nickel silicide film, and the p-type gate electrode includes a nickel silicide film. The hafnium silicate nitride films are not on the sidewalls of the gate electrodes.

REFERENCES:
patent: 6291282 (2001-09-01), Wilk et al.
patent: 6573134 (2003-06-01), Ma et al.
patent: 2003/0143825 (2003-07-01), Matsuo et al.
patent: 2000-252371 (2000-09-01), None
patent: 2003-045995 (2003-02-01), None
patent: 2003-258121 (2003-09-01), None
patent: 2003-303963 (2003-10-01), None
Chatterjee et al.; “Sub-100mn Gate Length Metal Gate MNOS Transistors Fabricated by a Replacement Gate Process”, 1997 IEEE; p. 821.
Yagashita et al.; “High Performance Metal Gate MOSFETs Fabricated by CMP for 0.1 μm Regime”, 1993 IEEE; pp. 29.3.1-29.3.4.
Krivokapic et al.; “Nickel Silicide Metal Gate FDSOI Devices with Improved Gate Oxide Leakage”, 2002 IEEE, pp. 271.
Maszara et al.; “Transistors with Dual Work Function Metal Gates by Single Full Silicidation (FUSI) of Polysilicon Gates”, 2002 IEEE, pp. 367.
Aoyama et al., “In-Situ HfSiON/SiO2 Gate Dielectric Fabrication Using Hot Wall Batch System”, IWGI 2003, Tokyo; pp. 174-179.

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