Semiconductor device with multi-layered wiring arrangement...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S014000

Reexamination Certificate

active

10981679

ABSTRACT:
A semiconductor device includes a semiconductor substrate having electronic elements produced therein, and an insulating underlayer formed thereon, and a multi-layered wiring arrangement constructed on the insulating underlayer semiconductor substrate. The multi-layered wiring arrangement includes a first insulating interlayer structure formed on the insulating underlayer, a second insulating interlayer structure, and a third insulating interlayer structure formed on the first insulating interlayer structure. Each of the first, second and third insulating interlayer structures includes a low-k insulating layer, and has a reinforcing element formed therein. The second insulating interlayer structure has a joint plug formed therein. The reinforcing elements of the first and third insulating interlayer structures are connected to each other through the joint plug.

REFERENCES:
patent: 6100589 (2000-08-01), Tanaka
patent: 6198170 (2001-03-01), Zhao
patent: 6222269 (2001-04-01), Usami
patent: 6297563 (2001-10-01), Yamaha
patent: 6492735 (2002-12-01), Matsubara
patent: 6576550 (2003-06-01), Brase et al.
patent: 6943431 (2005-09-01), Fukuyama et al.
patent: 2002/0017672 (2002-02-01), Ker, et al.
patent: 2002/0179991 (2002-12-01), Varrot, et al.
patent: 2004/0183162 (2004-09-01), Ohto et al.
patent: 2001-168093 (2001-06-01), None
patent: 2003-031611 (2003-01-01), None

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