Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-04-03
2007-04-03
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S005110, C714S006130, C714S042000, C714S718000, C365S201000
Reexamination Certificate
active
10734303
ABSTRACT:
A semiconductor memory comprises, a data memory having a plurality of memory regions to store data at addresses specified, a code memory having the same address space as the data memory to store error correction codes, an error correction code control circuit including an error correction code generation circuit, a syndrome generation circuit and an error correction code decoding circuit, generating an error correction code for correcting data before the data is written back into the memory region, and comparing the generated error correction code with corresponding error correction code, thereby to determine whether the data is erroneous, and an error correction code function invalidity control circuit invalidating an error correction function of the error correction code control circuit when the memory regions are accessed first after power application.
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Kiyohiro Furutani, et al., “A Built-in Hamming Code ECC Circuit for DRAM'S”, IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, pp. 50-56.
Beausoliel Robert
Ehne Charles
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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