Multi-bank memory accesses using posted writes

Details Multi-bank memory accesses using posted writes Multi-bank memory accesses using posted writes

Filed on

2007-05-29

Date issued

2007-05-29

Examiner

Bragdon, Reginald (Department: 2189)

Patent Class

Electrical computers and digital processing systems: memory

SubClass

Storage accessing and control

SubSubClass

Access timing

Other Related Categories

C711S168000, C711S169000, C365S233100, C365S230040

Type

Reexamination Certificate

Status

active

Patent number

11179784

Description

ABSTRACT:
Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

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