Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2007-09-18
2007-09-18
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S737000
Reexamination Certificate
active
11112108
ABSTRACT:
A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.
REFERENCES:
patent: 5731709 (1998-03-01), Pastore et al.
patent: 5830800 (1998-11-01), Lin
patent: 5841191 (1998-11-01), Chia et al.
patent: 5859475 (1999-01-01), Freyman et al.
patent: 6072239 (2000-06-01), Yoneda et al.
patent: 6093584 (2000-07-01), Fjelstad
patent: 6130115 (2000-10-01), Okumura et al.
patent: 6143981 (2000-11-01), Glenn
patent: 6228676 (2001-05-01), Glenn et al.
patent: 6229200 (2001-05-01), Mclellan et al.
patent: 6372540 (2002-04-01), Huemoeller
patent: 6444499 (2002-09-01), Swiss et al.
patent: 6514847 (2003-02-01), Ohsawa et al.
patent: 6578754 (2003-06-01), Tung
Huang Chien Ping
Huang Chih-Ming
Wang Yu-Po
Corless Peter F.
Edwards Angell Palmer & & Dodge LLP
Jensen Steven M.
Potter Roy
Siliconware Precision Industries Co. Ltd.
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