Method of making a planar double-gated transistor

Details Method of making a planar double-gated transistor Method of making a planar double-gated transistor

2007-04-10

2007-04-10

Ullah, Akm (Department: 2112)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C257S057000

Reexamination Certificate

active

11047448

ABSTRACT:
A silicon layer interposed between the top silicon nitride layer (SiN) and a silicon germanium layer (SiGe) which in turn is over a thick oxide (BOX) is selectively etched to leave a stack with a width that sets the gate length. A sidewall insulating layer is formed on the SiGe layer leaving the sidewall of the Si layer exposed. Silicon is epitaxially grown from the exposed silicon sidewall to form in-situ-doped silicon source/drain regions. The nitride layer is removed using the source/drain regions as a boundary for an upper gate location. The source/drain regions are coated with a dielectric. The SiGe layer is removed to provide a lower gate location. Both the upper and lower gate locations are filled with metal to form upper and lower gates for the transistor.

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