Flash memory programming to reduce program disturb

Details Flash memory programming to reduce program disturb Flash memory programming to reduce program disturb

2007-03-27

2007-03-27

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185140

Reexamination Certificate

active

11115681

ABSTRACT:
The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to array ground than the selected wordline, is biased at a voltage that is less than Vpass. The memory cells on this unselected wordline that are biased at this voltage block the gate induced drain leakage from the cells further up in the array. The remaining unselected wordlines are biased at Vpass. In another embodiment, a second source select gate line is added to the array. The source select gate line that is closest to the wordlines is biased at the voltage that is less than Vpassin order to block the gate induced drain leakage from the array.

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