Translation lookaside buffer-based memory system and method...

Details Translation lookaside buffer-based memory system and method... Translation lookaside buffer-based memory system and method...

2007-01-09

2007-01-09

Kim, Hong (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S005000, C711S109000

Reexamination Certificate

active

10037479

ABSTRACT:
A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial cabinet-to-cabinet communications path (MLINK). In some embodiments, the processor TLBs are located within one or more common memory sections, each memory section being connected to a plurality of processors, wherein each processor TLB is associated with one of the processors. The BTE performs efficient memory-to-memory data transfers without further processor intervention. The MLINK extends the BTE functionality beyond a single cabinet.

REFERENCES:
patent: 4513367 (1985-04-01), Chan et al.
patent: 5193166 (1993-03-01), Menasce
patent: 5255384 (1993-10-01), Sachs et al.
patent: 5301287 (1994-04-01), Herrell et al.
patent: 5784706 (1998-07-01), Oberlin et al.
patent: 5860025 (1999-01-01), Roberts et al.
patent: 5860110 (1999-01-01), Fukui et al.
patent: 5928353 (1999-07-01), Yamada
patent: 6182195 (2001-01-01), Laudon et al.
patent: 6226695 (2001-05-01), Kaiser et al.
patent: 6260131 (2001-07-01), Kikuta et al.
patent: 6370632 (2002-04-01), Kikuta et al.
patent: 6490671 (2002-12-01), Frank et al.
patent: 6496902 (2002-12-01), Faanes et al.
patent: 6629207 (2003-09-01), Yoshioka et al.
patent: 6686920 (2004-02-01), Peck et al.
patent: 6763327 (2004-07-01), Songer et al.
patent: 6779085 (2004-08-01), Chauvel
patent: 6859861 (2005-02-01), Rhodes
patent: 2001/0049742 (2001-12-01), Steely et al.
patent: 2002/0144061 (2002-10-01), Faanes et al.
patent: 2002/0169938 (2002-11-01), Scott et al.
patent: 0766177 (1997-04-01), None
Teller, P. J., et al., “Locating Multiprocessor TLBs at Memory”,Proceedings of the Twenty-Seventh Hawaii Internation Conference on Wailea, vol. I, 1) IEEE Computer Society 2) System Sciences, Architecture,(Jan. 4, 1994),554-563.
Brandt, M. , et al.,The Benchmarker's Guide for CRAY SV1 Systems, Cray Inc.,(Jul. 20, 2000),p. 1-39.

Affiliated with

Also associated with

Rating

Translation lookaside buffer-based memory system and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Translation lookaside buffer-based memory system and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Translation lookaside buffer-based memory system and method... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3751044