Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1999-03-22
2000-04-04
Wright, Norman Michael
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
711156, 714 5, G06F 1100, G06F 1300
Patent
active
060473924
ABSTRACT:
A system and method for tracking dirty memory which, in one embodiment, comprises a first memory corresponding to a first processor, a second memory corresponding to a second processor and a third memory coupled to the first memory, wherein the third memory stores bits corresponding to the pages of the first memory, and wherein each bit is set to "dirty" when the first processor writes to the corresponding page of the first memory and is set to "clean" when the corresponding page of the first memory is copied to a corresponding page of the second memory. The system and method can be used in a computer having multiple cpusets to assist in cpuset re-integration by copying the contents of one cpuset's memory to another cpuset's memory while the operating system of the computer continues to run.
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Liddell David C.
Williams Emrys J.
Berrier Mark L.
Revak Christopher A
Sun Microsystems Inc.
Wright Norman Michael
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