Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-08
2007-05-08
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10335239
ABSTRACT:
Some embodiments of the invention provide a method of solving an optimization problem. The problem includes a plurality of elements, and one or more solutions have been previously identified for each element. The method specifies a first solution set that has one identified solution for each element. In some embodiments, the method then iteratively examines all the elements of the problem. During the examination of each particular element, the method iteratively examines all the identified solutions for the particular element. During the examination of each particular solution, the method replaces the current solution for the particular element in the first solution set with a previously unexamined solution for the particular element if the replacement would improve the first set.
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U.S. Appl. No.
Frankle Jonathan
Teig Steven
Cadence Design Systems Inc.
Garbowski Leigh M.
Stattler Johansen & Adeli LLP
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