Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Capacitors

Reexamination Certificate

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Details

C365S189090, C365S233100, C365S230010, C257S301000, C257S302000

Reexamination Certificate

active

11397811

ABSTRACT:
Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

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U.S. Appl. No. 09/760,804, filed Jan. 17, 2001, pat. No. 6459113.

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