Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2007-09-18
2007-09-18
Trujillo, James K. (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S400000, C713S401000, C713S500000, C375S354000, C375S362000
Reexamination Certificate
active
10934462
ABSTRACT:
A circuit according to an embodiment of the present invention comprises a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a PLL circuit which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at an end point of the first clock distribution network, to a start point of the first clock distribution network, and a PLL circuit which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at an end point of the second clock distribution network, to a start point of the second clock distribution network.
REFERENCES:
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patent: 2000-347764 (2000-12-01), None
U.S. Appl. No. 11/373,113, filed Mar. 13, 2006, Oikawa.
Ian A. Young, et al., “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors”, IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1607.
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