Method of fabricating a semiconductor interconnect structure

Details Method of fabricating a semiconductor interconnect structure Method of fabricating a semiconductor interconnect structure

2007-09-18

2007-09-18

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S758000

Reexamination Certificate

active

10641540

ABSTRACT:
A method of fabricating a semiconductor interconnect structure is disclosed. The method includes forming a first metal plug in a first opening defined by a first layer of photoresist, forming a first metal layer in a second opening defined by a second layer of photoresist, forming a second metal plug in a third opening defined by a third layer of photoresist, forming a second metal layer on the third layer of photoresist, and removing the first, second and third layers of photoresist. The first metal plug is also formed in contact with a substrate assembly. The first metal layer is also formed in contact with the first metal plug. The second metal plug is also formed in contact with the first metal layer. The second metal layer is also formed in contact with the second metal plug.

REFERENCES:
patent: 4753896 (1988-06-01), Matloubian
patent: 5000818 (1991-03-01), Thomas et al.
patent: 5034799 (1991-07-01), Tomita et al.
patent: 5071518 (1991-12-01), Pan
patent: 5272111 (1993-12-01), Kosaki
patent: 5354712 (1994-10-01), Ho et al.
patent: 5391921 (1995-02-01), Kudoh et al.
patent: 5521121 (1996-05-01), Tsai et al.
patent: 5556812 (1996-09-01), Leuschner et al.
patent: 5639686 (1997-06-01), Hirano et al.
patent: 5686760 (1997-11-01), Miyakawa
patent: 5783864 (1998-07-01), Dawson et al.
patent: 5798559 (1998-08-01), Bothra et al.
patent: 5824599 (1998-10-01), Schacham-Diamand et al.
patent: 5834845 (1998-11-01), Stolmeijer
patent: 5843837 (1998-12-01), Baek et al.
patent: 5935868 (1999-08-01), Fang et al.
patent: 5950102 (1999-09-01), Lee
patent: 5953626 (1999-09-01), Hause et al.
patent: 5981374 (1999-11-01), Dalal et al.
patent: 6037248 (2000-03-01), Ahn
patent: 6069068 (2000-05-01), Rathore et al.
patent: 6130161 (2000-10-01), Ashley et al.
patent: 0 393 635 (1990-12-01), None
patent: 0 475 646 (1992-03-01), None
Carley, L., et al., “Fabrication and Performance of Mesa Interconnect,” Proceedings of the 1996 International Symposium on Low Power Electronics and Design, Aug. 1996, pp. 133-137.
Togo, M. et al., “A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs,” 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39.
Anand, M. et al., “NURA: A Feasible, Gas-Dielectric Interconnect Process,” 1996 Symposium on VLSI Technology Digets on Technical Papers, pp. 82-83.
Parameswaran, M. et al., “A New Approach for the Fabrication of Micromechanical Structures,” Sensors and Activators, vol. 19, pp. 289-307 (1989).

Affiliated with

Also associated with

Rating

Method of fabricating a semiconductor interconnect structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating a semiconductor interconnect structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a semiconductor interconnect structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3746501