Split gate storage device including a horizontal first gate...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S316000, C257SE29275, C257SE29305

Reexamination Certificate

active

11188603

ABSTRACT:
A split gate memory cell can include a first gate electrode and a second gate electrode. The split gate memory cell can also include a first diffusion region underlying a trench in a semiconductor substrate, wherein the trench has a sidewall, and the first diffusion region lies closer to the first gate electrode than the second gate electrode. The split gate memory cell can further include a second diffusion region lying outside the trench, wherein the second diffusion region lies closer to the second gate electrode than the first gate electrode. The split gate memory cell can still further include a charge storage layer adjacent to the sidewall of the trench, wherein the charge storage layer includes discontinuous storage elements. Methods of forming and using the split gate memory cell are also disclosed.

REFERENCES:
patent: 5705415 (1998-01-01), Orlowski et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6307782 (2001-10-01), Sadd et al.
patent: 6330184 (2001-12-01), White et al.
patent: 6399441 (2002-06-01), Ogura et al.
patent: 6583466 (2003-06-01), Lin et al.
patent: 6674120 (2004-01-01), Fujiwara
patent: 6706599 (2004-03-01), Sadd et al.
patent: 6818512 (2004-11-01), Hsieh
patent: 6894339 (2005-05-01), Fan et al.
patent: 7015537 (2006-03-01), Lee et al.
patent: 7112490 (2006-09-01), Hong et al.
patent: 2002/0151136 (2002-10-01), Lin et al.
patent: 2003/0062565 (2003-04-01), Yamazaki et al.
patent: 2003/0068864 (2003-04-01), Il-Yong et al.
patent: 2004/0000688 (2004-01-01), Harari et al.
patent: 2004/0121540 (2004-06-01), Lin
patent: 2004/0248371 (2004-12-01), Wang
patent: 2005/0037576 (2005-02-01), Chen et al.
patent: 2005/0259475 (2005-11-01), Forbes
patent: 2005/0280089 (2005-12-01), Forbes
patent: 2005/0280094 (2005-12-01), Forbes
patent: 2006/0152978 (2006-07-01), Forbes
patent: 2006/0166443 (2006-07-01), Forbes
Osabe, et al. “Charge-Injection Length in Silicon Nanocrystal Memory Cells,” VLSI, p. 242, 2004.
Ma, et al. “A Dual-Bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single-Vcc High Density Flash Memories,” IEDM, p. 57-60, 1994.
“Twin MONOS Cell with Dual Control Gates,” VLSI Technology, Source-Side Injection Cell with Two Storage Regions Forming in Nitride, p. 122, 2000.
“Vertical Floating-Gate 4.5/sup 2/split-gate NOR Flash Memory at 110nm Node,” VLSI Technology, Source-Side Injection Cell in a Trench, p. 72, 2004.
U.S. Appl. No. 10/961,295, filed Oct. 8, 2004.
U.S. Appl. No. 11/079,674, filed Mar. 14, 2005.
Lee, D., et al. “Vertical Floating-Gate 4.5F2 Split-Gate NOR Flash Memory at 110nm Node,” 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 72-73, 2004.
Van Houdt, J., et al. “An Analytical Model for the Optimization of Source-Side Injection Flash EEPROM Devices,” IEEE Transactions on Electron Devices, vol. 42, No. 7, pp. 1314-1320, Jul. 1995.
U.S. Appl. No. 11/188,935, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,999, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,953, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,898, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,910, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,909, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,591, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,939, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,588, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,584, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,615, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,582, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,583, filed Jul. 25, 2005.
U.S. Appl. No. 11/188,585, filed Jul. 25, 2005.
Hayashi, Y., et al. “Twin MONOS Cell with Dual Control Gates,” 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123, 2000.
Guan, H., et al. “An Analytical Model for Optimization of Programming Efficiency and Uniformity of Split Gate Source-Side Injection Superflash Memory,” IEEE Transactions on Electron Devices, vol. 50, No. 3, pp. 809-815, Mar. 2003.
U.S. Appl. No. 11/525,747, filed Sep. 22, 2006.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Split gate storage device including a horizontal first gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Split gate storage device including a horizontal first gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Split gate storage device including a horizontal first gate... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3743604

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.