Method and apparatus for identifying mechanisms responsible...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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C702S183000, C714S736000

Reexamination Certificate

active

10739827

ABSTRACT:
One embodiment of the present invention provides a technique for detecting anomalies during operation of a test computer system. Initially, a golden system and the test system are equipped with the same hardware configuration, wherein the golden system has gone through extensive qualification testing and is presumed to be operating correctly. Next, a deterministic load is executed on the golden system, and values for performance parameters from the golden system are monitored while the deterministic load is executing. Similarly, the deterministic load is also executed on the test system, and values for performance parameters from the test system are monitored while the deterministic load is executing. Next, pairwise differences are computed between values for performance parameters received from the test system and values for performance parameters received from the golden system. Finally, change detection techniques are applied to the pairwise differences to detect anomalies during operation of the test system.

REFERENCES:
patent: 4937763 (1990-06-01), Mott
patent: 5995915 (1999-11-01), Reed et al.
patent: 6324665 (2001-11-01), Fay
patent: 2001/0005821 (2001-06-01), Ottosson
patent: 2002/0175697 (2002-11-01), Miller et al.

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