Masked spacer etching for imagers

Details Masked spacer etching for imagers Masked spacer etching for imagers

2007-05-01

2007-05-01

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S072000, C257S291000, C257S431000

Reexamination Certificate

active

10921274

ABSTRACT:
The invention relates to a dual masked spacer etch for improved dark current performance in imagers. After deposition of spacer material such as oxide, N-channel regions are first opened for N+source/drain implant and P-channel regions are then opened for P+source/drain implant. Prior to the N+source/drain implant, the wafer receives a patterned first spacer etch. During this first spacer etch, the photosensor region is covered with resist. Prior to the P+source/drain implant, a masked second spacer etch is performed. Again the photosensor region is protected with photoresist. In such a manner, spacers are formed on the gates of both the N-channel and P-channel transistors but in the photodiode region the spacer insulator remains.

REFERENCES:
patent: 6194258 (2001-02-01), Wuu
patent: 6207565 (2001-03-01), Yeh et al.
patent: 6306678 (2001-10-01), Chiang et al.
patent: 6329233 (2001-12-01), Pan et al.
patent: 6541329 (2003-04-01), Chen et al.
patent: 6607951 (2003-08-01), Chen et al.
patent: 6720595 (2004-04-01), Clevenger et al.
patent: 2005/0056544 (2005-03-01), Liu et al.

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