Low-cost, low-voltage single-layer polycrystalline EEPROM...

Details Low-cost, low-voltage single-layer polycrystalline EEPROM... Low-cost, low-voltage single-layer polycrystalline EEPROM...

2007-04-24

2007-04-24

Tran, Long K. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257SE29170, C257SE29309, C438S201000, C438S288000, C438S573000

Reexamination Certificate

active

11136140

ABSTRACT:
An EEPROM memory transistor having a floating gate. The floating gate is formed using a BiCMOS process and has a first sinker dopant region proximate to a tunnel diode window, and a second sinker dopant region proximate to a coupling capacitor region. An optional third sinker region may be formed proximate to a source junction of the EEPROM memory transistor. Also, a shallow trench isolation (STI) region may be formed between the first and second sinker dopant regions.

REFERENCES:
patent: 5248624 (1993-09-01), Icel et al.
patent: 5909400 (1999-06-01), Bertin et al.
patent: 6022778 (2000-02-01), Contiero et al.
patent: 6025625 (2000-02-01), Chi
patent: 6172392 (2001-01-01), Schmidt et al.
patent: 6208559 (2001-03-01), Tu et al.
patent: 6438030 (2002-08-01), Hu et al.
patent: 6532170 (2003-03-01), Madurawe et al.

Affiliated with

Also associated with

Rating

Low-cost, low-voltage single-layer polycrystalline EEPROM... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low-cost, low-voltage single-layer polycrystalline EEPROM..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low-cost, low-voltage single-layer polycrystalline EEPROM... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3739483