Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2007-04-24
2007-04-24
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S593000, C257SE21179
Reexamination Certificate
active
10688965
ABSTRACT:
There are provided a gate dielectric film formed on a semiconductor substrate; a gate electrode including: a first electrode layer formed on the gate dielectric film, a dielectric film having a thickness of 5 Å or more and 100 Å or less, and formed on the first electrode layer, and a second electrode layer formed on the dielectric film; and a source and drain regions formed in the semiconductor substrate at both sides of the gate electrode.
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Notification of Reason for Rejection issued by the Japanese Patent Office, mailed Mar. 14, 2006, for Japanese Patent Application No. 203945/2003, and English-language translation thereof.
Decision of Rejection issued by the Japanese Patent Office on Jan. 30, 2007, in Japanese Patent Application No. 2003-203945, and English-language translation thereof.
Narita Masaki
Sasaki Toshiyuki
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Geyer Scott B.
Kabushiki Kaisha Toshiba
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