Dynamic programmable logic array having enable unit

Details Dynamic programmable logic array having enable unit Dynamic programmable logic array having enable unit

2007-07-17

2007-07-17

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S037000, C326S041000

Reexamination Certificate

active

11102161

ABSTRACT:
A DPLA (dynamic programmable logic array) uses an enable unit for each output line that provides OR-functionality, to eliminate a clock signal in the OR-plane. A clock signal is used only in the AND-plane for pre-charging the product term lines. Such a DPLA operates properly without a delay constraint between clock signals in both the AND-plane and the OR-plane for proper operation at higher frequencies.

REFERENCES:
patent: 5083047 (1992-01-01), Horie et al.
patent: 5412785 (1995-05-01), Skruhak et al.
patent: 5511173 (1996-04-01), Yamaura et al.
patent: 5719505 (1998-02-01), Ditlow et al.
Korean Patent Application No. 1019990063775 to Choi, having Publication date of Jul. 7, 2001 (w/ English Abstract page).
Korean Patent Application No. 1020020047229 to Lee, having Publication date of Feb. 14, 2004 (w/ English Abstract page).
Korean Patent Application No. 10-1996-0010748 having Publication date of Nov. 21, 1996 (w/ English Abstract page).
Korean Patent Application No. 05-242888 having Publication date of Apr. 24, 1995 (w/ English Abstract page).

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