Simultaneous planar and non-planar thin-film transistor...

Details Simultaneous planar and non-planar thin-film transistor... Simultaneous planar and non-planar thin-film transistor...

2007-07-03

2007-07-03

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C257SE51005, C257SE27100

Reexamination Certificate

active

10985587

ABSTRACT:
A method is provided for concurrently forming MP-TFTs and P-TFTs. Generally, the method comprises: forming a P-TFT having source/drain (S/D) regions, an intervening channel region, and a gate, all in a first horizontal plane; and simultaneously forming a MP-TFT having a first gate in the first horizontal plane and at least one S/D region in a second horizontal plane, overlying the first horizontal plane. The vertical TFT (V-TFT) is an MP-TFT having vertical first gate sidewalls and a vertical channel region overlying a gate sidewall. The dual-gate TFT (DG-TFT) is an MP-TFT having a bottom gate, first and second S/D regions with top surfaces, an intervening channel region with a top surface, and a second, top gate with a bottom surface, all in a second horizontal plane, overlying the first horizontal plane.

REFERENCES:
patent: 6603453 (2003-08-01), Yamazaki et al.
patent: 6960787 (2005-11-01), Yamazaki et al.

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