Method of buffer insertion to achieve pin specific delays

Details Method of buffer insertion to achieve pin specific delays Method of buffer insertion to achieve pin specific delays

2007-07-10

2007-07-10

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11041489

ABSTRACT:
A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as output a revised integrated circuit design that includes the buffer sub-tree.

REFERENCES:
patent: 6487697 (2002-11-01), Lu et al.
patent: 6564361 (2003-05-01), Zolotykh et al.
patent: 2004/0064793 (2004-04-01), Alpert et al.
patent: 2006/0010414 (2006-01-01), Lee et al.

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