Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-03-20
2007-03-20
Soward, Ida M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S019000, C257S288000, C257S328000, C257S331000, C257S618000, C257S623000
Reexamination Certificate
active
11039197
ABSTRACT:
An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.
REFERENCES:
patent: 5124777 (1992-06-01), Lee
patent: 5338959 (1994-08-01), Kim et al.
patent: 5346839 (1994-09-01), Sundaresan
patent: 5466621 (1995-11-01), Hisamoto et al.
patent: 5545586 (1996-08-01), Koh
patent: 5563077 (1996-10-01), Ha
patent: 5578513 (1996-11-01), Maegawa
patent: 5658806 (1997-08-01), Lin et al.
patent: 5701016 (1997-12-01), Burroughs et al.
patent: 5716879 (1998-02-01), Choi et al.
patent: 5827769 (1998-10-01), Aminzadeh et al.
patent: 5905285 (1999-05-01), Gardner et al.
patent: 6251751 (2001-06-01), Chu et al.
patent: 6252284 (2001-06-01), Muller et al.
patent: 6376317 (2002-04-01), Forbes et al.
patent: 6396108 (2002-05-01), Krivokapic et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6475869 (2002-11-01), Yu
patent: 6475890 (2002-11-01), Yu
patent: 6483156 (2002-11-01), Adkisson et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6562665 (2003-05-01), Yu
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6635909 (2003-10-01), Clark et al.
patent: 6645797 (2003-11-01), Buynoski et al.
patent: 6680240 (2004-01-01), Maszara
patent: 6706571 (2004-03-01), Yu et al.
patent: 6709982 (2004-03-01), Buynoski et al.
patent: 6716684 (2004-04-01), Krivokapic et al.
patent: 6716690 (2004-04-01), Wang et al.
patent: 6730964 (2004-05-01), Horiuchi
patent: 6756657 (2004-06-01), Zhang et al.
patent: 6764884 (2004-07-01), Yu et al.
patent: 6774390 (2004-08-01), Sugiyama et al.
patent: 6835618 (2004-12-01), Dakshina-Murthy
patent: 6838322 (2005-01-01), Pham et al.
patent: 6858472 (2005-02-01), Chau et al.
patent: 6858478 (2005-02-01), Chau et al.
patent: 6881635 (2005-04-01), Chidambarrao et al.
patent: 6884154 (2005-04-01), Mizushima et al.
patent: 6921982 (2005-07-01), Joshi et al.
patent: 6955969 (2005-10-01), Djomehri et al.
patent: 2002/0011612 (2002-01-01), Hieda
patent: 2002/0036290 (2002-03-01), Inaba et al.
patent: 2002/0081794 (2002-06-01), Ito
patent: 2002/0166838 (2002-11-01), Nagarajan
patent: 2002/0167007 (2002-11-01), Masahiko et al.
patent: 2003/0057486 (2003-03-01), Gambino et al.
patent: 2003/0085194 (2003-05-01), Hopkins, Jr.
patent: 2003/0098488 (2003-05-01), O'Keeffe et al.
patent: 2003/0102497 (2003-06-01), Fried et al.
patent: 2003/0111686 (2003-06-01), Nowak
patent: 2003/0122186 (2003-07-01), Sekigawa et al.
patent: 2003/0143791 (2003-07-01), Cheong et al.
patent: 2003/0151077 (2003-08-01), Mathew et al.
patent: 2003/0201458 (2003-10-01), Clark et al.
patent: 2003/0227036 (2003-12-01), Sugiyama et al.
patent: 2004/0031979 (2004-02-01), Lochtefeld et al.
patent: 2004/0036118 (2004-02-01), Adadeer et al.
patent: 2004/0036127 (2004-02-01), Chau et al.
patent: 2004/0061178 (2004-04-01), Lin-Ming-Ren et al.
patent: 2004/0092062 (2004-05-01), Ahmed et al.
patent: 2004/0092067 (2004-05-01), Hanafi et al.
patent: 2004/0094807 (2004-05-01), Chau et al.
patent: 2004/0099903 (2004-05-01), Yeo et al.
patent: 2004/0110097 (2004-06-01), Ahmed et al.
patent: 2004/0119100 (2004-06-01), Nowal et al.
patent: 2004/0126975 (2004-07-01), Ahmed et al.
patent: 2004/0145019 (2004-07-01), Dakshina-Murthy et al.
patent: 2004/0166642 (2004-08-01), Chen et al.
patent: 2004/0180491 (2004-09-01), Arai et al.
patent: 2004/0191980 (2004-09-01), Rios et al.
patent: 2004/0195624 (2004-10-01), Liu et al.
patent: 2004/0197975 (2004-10-01), Krivokapic et al.
patent: 2004/0198003 (2004-10-01), Yeo et al.
patent: 2004/0227187 (2004-11-01), Cheng et al.
patent: 2004/0238887 (2004-12-01), Nihey
patent: 2004/0253792 (2004-12-01), Cohen et al.
patent: 2004/0256647 (2004-12-01), Lee et al.
patent: 2004/0262683 (2004-12-01), Nihey
patent: 2004/0262699 (2004-12-01), Rios et al.
patent: 2005/0093067 (2005-05-01), Yeo et al.
patent: 2005/0093154 (2005-05-01), Kottantharayil et al.
patent: 2005/0118790 (2005-06-01), Lee et al.
patent: 2005/0127362 (2005-06-01), Zhang et al.
patent: 2005/0145941 (2005-07-01), Bedell et al.
patent: 2005/0156202 (2005-07-01), Rhee et al.
patent: 2005/0184316 (2005-08-01), Kim et al.
patent: 2005/0191795 (2005-09-01), Chidambarrao et al.
patent: 2005/0224797 (2005-10-01), Ko et al.
patent: 2005/0224798 (2005-10-01), Buss
patent: 2005/0224800 (2005-10-01), Lindert et al.
patent: 2005/0227498 (2005-10-01), Furukawa et al.
patent: 2005/0230763 (2005-10-01), Huang et al.
patent: 2006/0014338 (2006-01-01), Doris et al.
patent: 2006/0138548 (2006-06-01), Richards et al.
patent: 0623963 (1994-11-01), None
patent: 1 202 335 (2002-05-01), None
patent: 1 566 844 (2005-08-01), None
patent: 2002298051 (2003-10-01), None
patent: WO 02/43151 (2002-05-01), None
patent: WO 2004/059726 (2004-07-01), None
Jing Guo, et al. “Performance Projections for Ballistic Carbon Nanotube Field-Effect Transistors”, Appiled Physics Letters, vol. 80, No. 17, pp. 3192-3194 (Apr. 29, 2004).
Ali Javey, et al., “High-K Dielectrics for Advanced Carbon-Nanotube Transistors and Logic Gates”, Advance Online Publication, Published online, pp. 1-6 (Nov. 17, 2002).
Richard Martel, et al., “Carbon Nanotube Field Effect Transistors for Logic Applications” IBM, T.J. Watson Research Center, 2001 IEEE, IEDM 01, pp. 159-162.
David M. Fried, et al., “High-Performance P-Type Independent-Gate FinFETs, IEEE Electron Device Letters”, vol. 25, No. 4, Apr. 2004, pp. 199-201.
David M. Fried, et al., “Improved Independent Gate N-Type FinFET Fabrication and Characterization”, IEEE Electron Device Letters, vol. 24, No. 9, Sep. 2003, pp. 592-594.
Charles Kuo, et al. “A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications”, IEEE Transactions on Electron Devices, vol. 50, No. 12, Dec. 2003, pp. 2408-2416.
Charles Kuo, et al., “A Capacitorless Double-Gate DRAM Cell Design for High Density Applications”, 2002 IEEE International Electron Devices Meeting Technical Digest, Dec. 2002, pp. 843-846.
Takashi Ohsawa, et al., “Memory Design Using a One-Transistor Gain Cell on SOI”, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1510-1522.
T. Tanaka, et al., “Scalability Study on a Capacitorless 1T-DRAM: From Single-Gate PD-SOI to Double Gate FinDRAM”, 2004 IEEE International Electron Devices Meeting Technical Digest, Dec. 2004, 4 pages.
T. M. Mayer, et al., “Chemical Vapor Deposition of Fluoroalkylsilane Monolayer Films for Adhesion Control in Microelectromechanical Systems” 2000 American Vacuum Society B 18(5), Sep./Oct. 2000, pp. 2433-2440.
International Search Report PCT/US2005/000947, Int'l. filing date Jan. 10, 2005, mailed May 3, 2005 (7 pages).
T. Park et al., “Fabrication of Body-Tied FinFETs (Omega MOSFETS) Using Bulk Si Wafers”, 2003 Symposia on VLSI Technology Digest of Technical Papers, Jun. 2003, pp. 135-136.
Burenkov, A. et al., “Corner Effect Double and Triple Gate FINFETs”, European Solid-State Device Research, 2003 33rdConference on Essderc '03 Sep. 2003, Piscataway, NJ, USA, IEEE, pp. 135-138, XP010676716.
Chang, S.T. et al, “3-D Simulation of Strained Si/SiGe Heterojunction FinFETS”, Semiconductor Device Research Symposium, 2003 International, Dec. 2003, Piscataway, NJ, USA, IEEE, pp. 176-177, XP010687197.
Subramanian et al, “A Bulk Si-Compatible Ultrathin-Body SOI Technology for Sub- 100nm MOSFETS”, Proceedings of the 57th Annual Device REach Conference, pp. 28-29 (1999).
Hisamoto et al, “A Folded-Channel MOSFET for Deepsub-tenth Micron ERa”, 1998 IEEE International Electron Device Meeting Technical Digest, pp. 1032-1034 (1998).
Huang et al, “Sub 50 nm FinFet:
Chau Robert
Datta Suman
Doyle Brian S.
Jin Been-Yih
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Soward Ida M.
LandOfFree
Non-planar MOS structure with a strained channel region does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-planar MOS structure with a strained channel region, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-planar MOS structure with a strained channel region will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3730885