Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1997-12-16
2000-03-07
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711154, 711156, 711169, 711172, 711163, 709214, G06F 1300
Patent
active
060353783
ABSTRACT:
A method, implemented in hardware, to successively obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within a specified address range within system memory. Whenever the processing node generates a transaction requiring access to a memory address within the specified address range, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. The specified address range is defined by an address value contained within a range counter. The range counter is initially loaded with a starting address value, defining a first group of page addresses to monitor. This address value is periodically incremented up to a preset maximum address value to define successive groups of page addresses to be monitored. Thus, a record of memory access patterns to successive portions of system memory is created which can be used to optimize memory and process assignments in the computer system.
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Bataille Pierre-Michel
Cabeca John W.
NCR Corporation
Stover James M.
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