Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-10-21
2000-03-07
Peikari, B. James
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711103, 711144, 711163, G06F 1214
Patent
active
060353767
ABSTRACT:
A system for converting between the states of fresh and owned in a multi-processor computer system comprises a memory line with a structure including a first field for storing a memory state, a second field for storing an address, and a third field for storing data. Each of the cache lines for processors in the system includes a plurality of data fields including one for storing the cache line state, one for storing a forward pointer, one for storing a backward pointer, and one for storing data. A method is also provided for automatically washing memory lines. The system is advantageous because it allows the data to be transferred immediately when it is available, rather than requiring the next cache-line owner to poll until the data is available. Still more particularly, the present invention provides a method of reliably converting an owned data line from stale to fresh when read fresh accesses are being performed, while correctly leaving the line in an owned state if additional read owned access occur. The present invention maximizes the efficiency of memory by maintaining a fresh copy of the data line when the data is only being read, and maintaining an owned copy of the data line when the data is being read and written.
REFERENCES:
patent: 5023854 (1991-06-01), Satoh et al.
patent: 5463759 (1995-10-01), Ghosh et al.
patent: 5469555 (1995-11-01), Ghosh et al.
patent: 5956754 (1999-09-01), Kimmel
Apple Computer Inc.
Peikari B. James
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