Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-08
2007-05-08
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
11078781
ABSTRACT:
A method is disclosed for completing a flip chip package design by re-using mask designs in a tool library. The method comprises analyzing one or more input/out bump locations of a chip, analyzing one or more solder ball locations of a package hosting the chip with regard to a predetermined printed circuit board, and designing the package hosting the chip by using a tool library containing one or more existing mask designs for re-use, wherein when one or more existing mask designs are used for the package, at least one custom connection layer of the package is redesigned when needed for connecting the chip to the printed circuit board without producing a full set of new masks for the package.
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Chiang Jack
Dimyan Magid Y.
K & L Gates LLP
Taiwan Semiconductor Manufacturing Co. Ltd.
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