Method for reducing leakage current of LSI

Details Method for reducing leakage current of LSI Method for reducing leakage current of LSI

2007-01-23

2007-01-23

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S323000, C713S324000

Reexamination Certificate

active

09901083

ABSTRACT:
There is disclosed a method for reducing leakage current of an LSI, which enables information not memory-mapped in the address of a CPU to be easily saved, and information saving and returning to be carried out by simple switching operations without needing any special switching operations by the CPU. An LSI chip is divided into two parts, namely a main power supply region and a backup power supply region. A scan path is provided to interconnect memory units including a CPU, a CPU peripheral circuit and so on, in the main power supply region. When an operation standby state is set, a scanning operation through the scan path is started, information held in the memory units of each of the circuits in the main power supply region is read, and then thus read information is saved in an storage section in the backup power supply region.

REFERENCES:
patent: 6363501 (2002-03-01), Tobias et al.
patent: 6535982 (2003-03-01), Kawabe et al.
patent: 6684275 (2004-01-01), Goldstein
patent: A 5-108194 (1993-04-01), None
patent: A 6-52686 (1994-02-01), None
“IEEE Standard Test Access Port and Boundary-Scan Architecture”, 1993, Institute of Electrical and Electronics Engineers, Inc., pp. 9-14.

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