Method and circuit for interlacing numeric data to reduce...

Details Method and circuit for interlacing numeric data to reduce... Method and circuit for interlacing numeric data to reduce...

2007-01-09

2007-01-09

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

10424166

ABSTRACT:
A method for interlacing digital data to reduce transmission errors includes dividing a stream of digital data into consecutive blocks of bits, and interlacing each block of bits by writing to an interlacing table. The interlacing table is arranged in the form of rows and columns of memory addresses, with a number of the rows and columns corresponding to predetermined interlacing parameters. The access sequences to the memory addresses for interlacing the blocks of bits are different from each other. The method further includes reading a block of bits in the interlacing table according to a memory addresses access sequence, and also writing bits to a consecutive block of bits according to the memory addresses access sequence during the reading.

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Patent Abstracts of Japan, vol. 1997, No. 02, Feb. 28, 1997, & JP 08279766A (Nec Corp.), Oct. 22, 1996.

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