Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2007-05-08
2007-05-08
Elms, Richard T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
C365S189030, C365S189050, C365S189090
Reexamination Certificate
active
11061035
ABSTRACT:
A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data signals to generate corresponding timed read data signals. These timed data signals and termination signals from the timing circuit are applied to pull-up and pull-down circuitry, which drive respective pull-up and pull-down transistors coupled to the data bus terminals. The transistors drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected. Additionally, the pull-up and pull-down transistors bias the data bus terminals to respective voltages corresponding to the selected operating mode.
REFERENCES:
patent: 5097149 (1992-03-01), Lee
patent: 5099148 (1992-03-01), McClure et al.
patent: 5128560 (1992-07-01), Chern et al.
patent: 5134311 (1992-07-01), Biber et al.
patent: 5274276 (1993-12-01), Casper et al.
patent: 5576656 (1996-11-01), McClure
patent: 5594373 (1997-01-01), McClure
patent: 5606275 (1997-02-01), Farhang et al.
patent: 5617064 (1997-04-01), Gorecki
patent: 5729152 (1998-03-01), Leung et al.
patent: 5732027 (1998-03-01), Arcoleo et al.
patent: 5754480 (1998-05-01), Sato
patent: 5834951 (1998-11-01), Klein
patent: 5864506 (1999-01-01), Arcoleo et al.
patent: 5903504 (1999-05-01), Chevallier et al.
patent: 5926031 (1999-07-01), Wallace et al.
patent: 5949254 (1999-09-01), Keeth
patent: 5995443 (1999-11-01), Farmwald et al.
patent: 6026456 (2000-02-01), Ilkbahar
patent: 6060907 (2000-05-01), Vishwanthaiah et al.
patent: 6066977 (2000-05-01), Felton et al.
patent: 6069504 (2000-05-01), Keeth
patent: 6087853 (2000-07-01), Huber et al.
patent: 6198307 (2001-03-01), Garlepp et al.
patent: 6222388 (2001-04-01), Bridgewater
patent: 6236255 (2001-05-01), Oguri
patent: 6288563 (2001-09-01), Muljono et al.
patent: 6307424 (2001-10-01), Lee
patent: 6307791 (2001-10-01), Otsuka et al.
patent: 6323687 (2001-11-01), Yano
patent: 6330194 (2001-12-01), Thomann et al.
patent: 6339351 (2002-01-01), Ang et al.
patent: 6351138 (2002-02-01), Wong
patent: 6351421 (2002-02-01), Merritt
patent: 6359465 (2002-03-01), Hui
patent: 6373276 (2002-04-01), Hui
patent: 6388495 (2002-05-01), Roy et al.
patent: 6420913 (2002-07-01), Ang et al.
patent: 6424169 (2002-07-01), Partow et al.
patent: 6445245 (2002-09-01), Schultz et al.
patent: 6445316 (2002-09-01), Hsu et al.
patent: 6456124 (2002-09-01), Lee et al.
patent: 6459320 (2002-10-01), Lee
patent: 6466487 (2002-10-01), Otsuka
patent: 6480798 (2002-11-01), Lee
patent: 6501306 (2002-12-01), Kim et al.
patent: 6549036 (2003-04-01), Lee
patent: 6563337 (2003-05-01), Dour
patent: 6643789 (2003-11-01), Mullarkey
patent: 6657906 (2003-12-01), Martin
patent: 6700418 (2004-03-01), Yu et al.
patent: 6711073 (2004-03-01), Martin
patent: 6885226 (2005-04-01), Waldrop
patent: 2004/0017696 (2004-01-01), Allen et al.
patent: 2004/0141380 (2004-07-01), Kim et al.
Janzen Jeffrey W.
Morzano Christopher
Dorsey & Whitney LLP
Elms Richard T.
Le Toan
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