Method for optimizing integrated circuit device design and...

Details Method for optimizing integrated circuit device design and... Method for optimizing integrated circuit device design and...

2007-07-17

2007-07-17

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

10966492

ABSTRACT:
Improved analysis and refinement of integrated circuit device design and other programs is facilitated by methods in which an original program is partitioned into subprograms representing valid computational paths; each subprogram is refined when cyclic dependencies are found to exist between the variables; computational paths whose over-approximated reachable states are found to be contained in another computational path are merged; and finally, the remaining subprograms conjoined decision conditions become candidates for hints for program refinement.

REFERENCES:
patent: 6484134 (2002-11-01), Hoskote
patent: 6643827 (2003-11-01), Yang
patent: 7058910 (2006-06-01), Bharadwaj et al.

Affiliated with

Also associated with

Rating

Method for optimizing integrated circuit device design and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for optimizing integrated circuit device design and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for optimizing integrated circuit device design and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3722031