Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-03-06
2007-03-06
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185260, C365S185280, C365S230060, C257S017000, C257S135000, C257S302000
Reexamination Certificate
active
10931711
ABSTRACT:
Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the output lines form an array. A number of logic cells are formed at the intersections of output lines and address lines. Each of the logic cells includes a floating gate transistor which includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposing the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5and/or a Perovskite oxide tunnel barrier.
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Pham Ly Duy
Schwegman Lundberg Woessner & Kluth P.A.
Zarabian Amir
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