Programmable element latch circuit

Details Programmable element latch circuit Programmable element latch circuit

Filed on

2006-12-05

Date issued

2006-12-05

Examiner

Do, Thuan (Department: 2825)

Patent Class

Computer-aided design and analysis of circuits and semiconductor

SubClass

Nanotechnology related integrated circuit design

Other Related Categories

C716S030000, C703S014000

Type

Reexamination Certificate

Status

active

Patent number

07146585

Description

ABSTRACT:
An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch devices are designed such that a redundancy pretest cannot be performed on the antifuse latch device once the antifuses are programmed but rather requires additional circuitry to map the appropriate address bits to test the redundant row or column. The present invention adds a level translating inverter to a conventional antifuse latch device, thus allowing the antifuse latch device to simulate an unblown antifuse by isolating the antifuse from the latch.

REFERENCES:
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5631862 (1997-05-01), Cutter et al.
patent: 5838624 (1998-11-01), Pilling et al.
patent: 5978298 (1999-11-01), Zheng
patent: 5999480 (1999-12-01), Ong et al.
patent: 6064617 (2000-05-01), Ingalls
patent: 6130834 (2000-10-01), Mullarkey et al.

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