Method and apparatus for partial memory power shutoff

Details Method and apparatus for partial memory power shutoff Method and apparatus for partial memory power shutoff

2006-08-29

2006-08-29

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C713S320000, C345S582000, C345S211000, C345S520000, C361S697000

Reexamination Certificate

active

07100013

ABSTRACT:
A method for managing host system power consumption is provided. The host system includes host memory and external memory. The method initiates with providing a processor in communication with a memory chip over a bus. The memory chip is external memory. Then, a usage measurement of the external memory is determined. If the usage measurement is below a threshold value, the method includes copying data from the memory chip to the host memory and terminating power to the memory chip. In one embodiment, the power is terminated to at least one bank of memory in the memory chip. In another embodiment, an amount of reduction of the external memory can be determined rather than a usage measurement. In yet another embodiment, an address map is reconfigured in order to maintain a contiguous configuration. A graphical user interface and a memory chip are provided also.

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