Magnetic random access memory

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE21665, C257SE43004, C365S171000, C365S173000

Reexamination Certificate

active

07095071

ABSTRACT:
According to an aspect of the present invention, there is disclosed a magnetic resistive element comprising a first magnetic layer whose magnetized state changes in accordance with data, a nonmagnetic layer disposed on the first magnetic layer, and a second magnetic layer which is disposed on the nonmagnetic layer and whose magnetized state is fixed, wherein the first magnetic layer has a cross shape in which a maximum length of a first direction is L1and a maximum length of a second direction crossing the first direction at right angles is L2, and the second magnetic layer has a tetragonal shape in which the maximum length of the first direction is L3(≦L1) and the maximum length of the second direction is L4(<L2).

REFERENCES:
patent: 5650958 (1997-07-01), Gallagher et al.
patent: 6081445 (2000-06-01), Shi et al.
patent: 6518588 (2003-02-01), Parkin et al.
patent: 6545906 (2003-04-01), Savtchenko et al.
patent: 6833278 (2004-12-01), Deak
patent: 2004/0227172 (2004-11-01), Park
patent: 2005/0199926 (2005-09-01), Fukuzumi et al.
patent: 2002-170376 (2002-06-01), None
U.S. Appl. No. 11/232,017, filed Sep. 22, 2005, Fukuzumi.
U.S. Appl. No. 11/224,094, filed Sep. 13, 2005, Fukuzumi.
U.S. Appl. No. 11/245,353, filed Oct. 7, 2005, Nakayama et al.
M. Durlam, et al., “A low power 1Mbit based on 1T1MTJ bit cell integrated with Copper Interconnects”, IEEE Symposium on VLSI Circuits Digest of Technical Papers, 2002, 4 Pages.
Takeshi Honda, et al., “MRAM-Writing Circuitry to Compensate for Thermal-Variation of Magnetization-Reversal Current”, IEEE Symposium on VLSI Circuits Digest of Technical Papers, 2002, pp. 156-157.
Roy Scheuerlein, et al., “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell,”, ISSCC Technical Digest, 2000, 6 Pages.
A. Bette, et al., “A High-Speed 128Kbit MRAM Core for Future Universal Memory Application”, Symposium on VLSI Circuits Digest of Technical Papers, 2003, pp. 217-220.
A. R. Sitaram, et al., “A 0.18μm Logic-based MRAM Technology for High Performance Nonvolatile Memory Applications”, Symposium of VLSI Circuits Digest of Technical Papers, 0.14, Jul. 2003, pp. 15-16.
Gitae Jeong, et al., “A 0.24μm 2.0V 1T1MTJ 16kb NV Magnetoresistance RAM with Self Reference Sensing”, ISSCC 2003/ Session 16 / Non-Volatile Memory / Paper 16.2, IEEE International Solid-State Circuits Conference, 2003, 6 Pages.
M. Durlam, et al., “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC 2000 / Session 7/ TD: Emerging Memory & Device Technologies / Paper TA 7.3, IEEE International Solid-State Circuits Conference, 2000, 6 Pages.

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