Generating fast logic simulation models for a PLD design...

Details Generating fast logic simulation models for a PLD design... Generating fast logic simulation models for a PLD design...

2006-10-31

2006-10-31

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07131091

ABSTRACT:
Various approaches for generating a clock accurate simulation model from a circuit design description are disclosed. In one approach, a graph representation of the circuit design description is created. The graph representation includes nodes and edges. From the nodes in the graph representation, a plurality of register nodes are generated to correspond to respective register functions. Logic optimization is performed on nodes that represent combinational logic functions. For each register node and each output node, an evaluation equation is generated after performing logic optimization. For each clock cycle of a logic simulation, each evaluation equation is evaluated and produces an output value for the next clock cycle.

REFERENCES:
patent: 5648909 (1997-07-01), Biro et al.
patent: 6324678 (2001-11-01), Dangelo et al.
patent: 6385759 (2002-05-01), Batarekh
patent: 6591402 (2003-07-01), Chandra et al.
patent: 6606734 (2003-08-01), Greaves
patent: 6622287 (2003-09-01), Henkel
patent: 2004/0225970 (2004-11-01), Oktem
Raimund Ubar, Joan Raik, Adam Morawiec; “Back-Tracing and Event-Driven Techniques in High-Level Simulation with Decision Diagrams”; ISCAS 2000—IEEE International Symposium on Circuits and Systems; May 28-31, 2000; pp. I-208-I-211.
Samir Palnitkar, Darrell Parham; “Cycle Simulation Techniques”; 1995 IEEE; pp. 2-8.

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