Integrated circuit with self-aligned line and via and...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S675000, C438S700000, C257S774000

Reexamination Certificate

active

07119010

ABSTRACT:
An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

REFERENCES:
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patent: 6127263 (2000-10-01), Parikh
patent: 6133139 (2000-10-01), Dalal et al.
patent: 6143640 (2000-11-01), Cronin et al.
patent: 6153514 (2000-11-01), Wang et al.
patent: 6316351 (2001-11-01), Chen et al.
patent: 6337269 (2002-01-01), Huang et al.
patent: 6475810 (2002-11-01), Zhou et al.
patent: 2003/0040172 (2003-02-01), Brennam
patent: 1 928 460 (2000-08-01), None
patent: 1184903 (2000-08-01), None

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