Methods and apparatus for scan insertion

Details Methods and apparatus for scan insertion Methods and apparatus for scan insertion

2006-12-26

2006-12-26

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07155687

ABSTRACT:
In accordance with the present electronic design automation (EDA) for integrated circuits invention prior to synthesis, dummy elements are added to the library and an internal scan clock pin with no connections is provided. Then the design is synthesized, scan insertion is performed (defining scan chains, inserting chains), and the scan clock is connected to all flip-flops SCLK pins. Finally, the dummy elements are replaced with real gates and clock tree insertion is performed after placing the cell in a layout.

REFERENCES:
patent: 5285153 (1994-02-01), Ahanin et al.
patent: 6389566 (2002-05-01), Wagner et al.
patent: 6434735 (2002-08-01), Watkins
patent: 6957403 (2005-10-01), Wang et al.
patent: 2005/0022083 (2005-01-01), Wagner et al.

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