Sequential nibble burst ordering for data

Details Sequential nibble burst ordering for data Sequential nibble burst ordering for data

2006-08-01

2006-08-01

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S167000, C711S204000, C711S213000

Reexamination Certificate

active

07085912

ABSTRACT:
Methods of operating a memory device comprised of a plurality of arrays of memory cells and peripheral devices for reading and writing information to the memory cells. One method comprises outputting an n-bit word in two ½n bit prefetch steps from a plurality of memory arrays in response to an address bit. Another method comprises prefetching a first portion of a word from a memory array, and prefetching a second portion of the word from the memory array, the first and second portions being determined by an address bit. Another method comprises reading a word from a memory array in at least two prefetch operations, wherein the order of the prefetch operations is controlled by an address bit.

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