Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-01
2006-08-01
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C326S038000, C326S039000, C326S041000, C326S047000
Reexamination Certificate
active
07086025
ABSTRACT:
The interconnect pin count between field programmable gate arrays (FPGAS) used in prototyping an application specific integrated circuit (ASIC) is reduced without compromising the prototyping by using serial links between the FPGAs. A block A of the ASIC is programmed in a first FPGA. A block B of the ASIC is programmed in a second FPGA. Blocks A and B are identical between ASIC and FPGA implementations. Block A communicates with block B via two interconnected wrappers, which are, in this example, serial COM wrappers connected by a serial link.
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Adaptec, Inc.
Gunnison Forrest
Gunnison McKay & Hodgson, L.L.P.
Rossoshek Helen
Siek Vuthe
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