Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2006-02-21
2006-02-21
Tran, Thien F. (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S151000, C438S157000, C438S159000, C438S176000, C438S283000
Reexamination Certificate
active
07001801
ABSTRACT:
In order to increase an aperture ratio, a part of or all of a gate electrode that overlaps with channel formation regions (213, 214) of a pixel TFT is caused to overlap with second wirings (source line or drain line) (154, 157). Additionally, a first interlayer insulating film (149) and a second interlayer insulating film (150c) are disposed between the gate electrode and the second wirings (154, 157) so as to decrease a parasitic capacitance.
REFERENCES:
patent: 5177592 (1993-01-01), Takahashi et al.
patent: 5594569 (1997-01-01), Konuma et al.
patent: 5643826 (1997-07-01), Ohtani et al.
patent: 5712495 (1998-01-01), Suzawa
patent: 5717224 (1998-02-01), Zhang
patent: 5923962 (1999-07-01), Ohtani et al.
patent: 6057904 (2000-05-01), Kim et al.
patent: 6088070 (2000-07-01), Ohtani et al.
patent: 6165824 (2000-12-01), Takano et al.
patent: 6271897 (2001-08-01), Ichikawa et al.
patent: 6294799 (2001-09-01), Yamazaki et al.
patent: 6297520 (2001-10-01), Kubo et al.
patent: 6306694 (2001-10-01), Yamazaki et al.
patent: 6313481 (2001-11-01), Ohtani et al.
patent: 6365915 (2002-04-01), Hirai et al.
patent: 1 103 946 (2001-05-01), None
patent: 7-130652 (1995-05-01), None
patent: 09219453 (1997-08-01), None
patent: 10-247735 (1998-09-01), None
patent: 11-097702 (1999-04-01), None
patent: 11-133463 (1999-05-01), None
patent: 2000-299469 (2000-10-01), None
patent: 2000-312007 (2000-11-01), None
patent: 2001-343933 (2001-12-01), None
Yoshida, T. et al, “A Full-Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time,” SID 97 Digest, pp. 841-844, (1997).
Furue, H. et al, “Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability,” SID 98 Digest, pp. 782-785, (1998).
Shimokawa, R. et al, “Characterization of High-Efficiency Cast-Si Cell Wafers by MBIC Measurement,” Japanese Journal of Applied Physics, vol. 27, No. 5, pp. 751-758, May, (1998).
Suzawa Hideomi
Yamagata Hirokazu
Yamazaki Shunpei
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Semiconductor Energy Laboratory Co,. Ltd.
Tran Thien F.
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