Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-10-10
2006-10-10
Soward, Ida M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S315000, C257S317000, C257S318000, C257S319000, C257S320000, C257S321000, C257S322000, C257S323000, C257S324000, C257S325000, C257S326000, C257S386000, C257S392000, C257S548000, C257S504000, C257S545000
Reexamination Certificate
active
07119393
ABSTRACT:
A floating-gate transistor for an integrated circuit is formed on a p-type substrate. An n-type region is disposed over the p-type substrate. A p-type region is disposed over the n-type region. Spaced apart n-type source and drain regions are disposed in the p-type region forming a channel therein. A floating gate is disposed above and insulated from the channel. A control gate is disposed above and insulated from the floating gate. An isolation trench disposed in the p-type region and surrounding the source and drain regions, the isolation trench extending down into the n-type region. The substrate, the n-type region and the p-type region each biased such that the p-type region is fully depleted.
REFERENCES:
patent: 5359219 (1994-10-01), Hwang
patent: 5457652 (1995-10-01), Brahmbhatt
patent: 5471082 (1995-11-01), Maeda
patent: 5487033 (1996-01-01), Keeney et al.
patent: 5559044 (1996-09-01), Williams et al.
patent: 5635754 (1997-06-01), Strobel et al.
patent: 5726477 (1998-03-01), Williams et al.
patent: 5751631 (1998-05-01), Liu et al.
patent: 5822243 (1998-10-01), Shone
patent: 5837554 (1998-11-01), Contiero et al.
patent: 5838048 (1998-11-01), Hirai et al.
patent: 5854099 (1998-12-01), Farrenkopf
patent: 5874767 (1999-02-01), Terashima et al.
patent: 5960272 (1999-09-01), Ishimaru
patent: 5978276 (1999-11-01), Wong
patent: 6009017 (1999-12-01), Guo et al.
patent: 6023293 (2000-02-01), Watanabe et al.
patent: 6060742 (2000-05-01), Chi et al.
patent: 6100557 (2000-08-01), Hung et al.
patent: 6133604 (2000-10-01), Chi
patent: 6134150 (2000-10-01), Hsu et al.
patent: 6169693 (2001-01-01), Chan et al.
patent: 6187635 (2001-02-01), Kaya
patent: 6324102 (2001-11-01), McCollum
patent: 6329246 (2001-12-01), Lee
patent: 6417542 (2002-07-01), Werner
patent: 6492206 (2002-12-01), Hawley et al.
patent: 6501685 (2002-12-01), Hsu et al.
patent: 6617632 (2003-09-01), Taniguchi et al.
patent: 6624026 (2003-09-01), Liu et al.
patent: 6887758 (2005-05-01), Chindalore et al.
patent: 6908818 (2005-06-01), Hsu et al.
patent: 6952031 (2005-10-01), Yamauchi
patent: 2002/0031882 (2002-03-01), Uchida
patent: 2002/0113286 (2002-08-01), Shimizu
patent: 2002/0153546 (2002-10-01), Verhaar
patent: 2004/0000681 (2004-01-01), Shinohara et al.
patent: 2004/0026749 (2004-02-01), Ohsawa
patent: 2004/0065922 (2004-04-01), Wang
patent: 2005/0180215 (2005-08-01), Shum et al.
patent: 61123171 (1986-06-01), None
Actel Corporation
Sierra Patent Group Ltd
Soward Ida M.
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