Semiconductor memory having an arrangement of memory cells

Details Semiconductor memory having an arrangement of memory cells Semiconductor memory having an arrangement of memory cells

2006-06-06

2006-06-06

Weiss, Howard (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

07057224

ABSTRACT:
A semiconductor memory can have first lines to which memory cells are connected and that run divergently with respect to one another, and second lines to which the memory cells are connected that are curved. Combining the geometry of the memory cell array with storage capacitors laterally offset allows signal delays along word lines and bit lines to be aligned regardless of the position of a memory cell in the memory cell array. The geometry of the memory cell array allows short signal propagation times to be attained particularly along the first lines, which are divergent with respect to one another, this simplifying error-free operation of a semiconductor memory particularly at high clock frequencies.

REFERENCES:
patent: 6010953 (2000-01-01), Prall
patent: 6097621 (2000-08-01), Mori
patent: 6166941 (2000-12-01), Yoshida et al.
patent: 2002/0130384 (2002-09-01), Aton
patent: 10189919 (1998-07-01), None

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