Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

2006-02-07

2006-02-07

Lee, Hsien-Ming (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S319000, C257S324000

Reexamination Certificate

active

06995420

ABSTRACT:
A semiconductor device of the present invention has memory cells. Each of the memory cells includes a word gate formed over a semiconductor substrate with a first gate insulating layer interposed therebetween, an impurity layer, and first and second control gates in a shape of sidewalls. Each of the first and second control gates has a rectangular or square cross-sectional shape.

REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5422504 (1995-06-01), Chang et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5663923 (1997-09-01), Baltar et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6413821 (2002-07-01), Ebina et al.
patent: 6518124 (2003-02-01), Ebina et al.
patent: 6531350 (2003-03-01), Satoh et al.
patent: 6627491 (2003-09-01), Ebina et al.
patent: 6709922 (2004-03-01), Ebina et al.
patent: 2002/0100929 (2002-08-01), Ebina et al.
patent: 2003/0057505 (2003-03-01), Ebina et al.
patent: 2003/0058705 (2003-03-01), Ebina et al.
patent: 2003/0157767 (2003-08-01), Kasuya
patent: 2003/0166320 (2003-09-01), Kasuya
patent: 2003/0166321 (2003-09-01), Kasuya
patent: 2003/0166322 (2003-09-01), Kasuya
patent: 2003/0186505 (2003-10-01), Shibata
patent: 2003/0190805 (2003-10-01), Inoue
patent: 2003/0211691 (2003-11-01), Ueda
patent: 2004/0072402 (2004-04-01), Inoue
patent: 2004/0072403 (2004-04-01), Inoue
patent: 2004/0077145 (2004-04-01), Inoue
patent: 2004/0097035 (2004-05-01), Yamamukai
patent: 2004/0129972 (2004-07-01), Kasuya
patent: 2004/0132247 (2004-07-01), Kasuya
patent: 2004/0135196 (2004-07-01), Kasuya
patent: 7-161851 (1995-06-01), None
patent: A-11-8325 (1999-01-01), None
patent: 2978477 (1999-09-01), None
patent: A-2001-148434 (2001-05-01), None
patent: 2001-156188 (2001-06-01), None
patent: A-2002-231830 (2002-08-01), None
Hayashi, Yutaka et al., “Twin MONOS Cell with Dual Control Gates,” 2000 IEEE VLSI Technology Digest.
Chang, Kuo-Tung et al., “A New SONOS Memory Using Source-Side Injection for Programming,” IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 253-255.
Chen, Wei-Ming et al., “A Novel Flash Memory Device withS Plit Gate Source SideInjection and ONO Charge Storage Stack (SPIN),” 1997 VLSI Technology Digest, pp. 63-64.
U.S. Appl. No. 10/690,025, filed Oct. 22, 2003, Kasuya.

Affiliated with

Also associated with

Rating

Semiconductor device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing the same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3704096