Thin film transistor array substrate, manufacturing method...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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Details

C438S030000, C349S042000, C349S043000

Reexamination Certificate

active

07056777

ABSTRACT:
A thin film transistor array substrate including a gate pattern having a gate electrode, a gate line connected to the gate electrode, and a gate pad connected to the gate line, a source/drain pattern having a source electrode, a drain electrode, a data line connected to the source electrode, and a data pad connected to the data line, a gate insulating pattern formed along a matrix pattern including the gate pattern and the source/drain pattern except for a pixel area, a semiconductor pattern formed on the gate insulating pattern having a same pattern as the gate insulating pattern and partially removed at a thin film transistor area and the gate line area, and a transparent electrode pattern having a pixel electrode formed at the pixel area and connected to the drain electrode, a gate pad protective electrode formed on the gate pad, and a data pad protective electrode formed on the data pad.

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patent: 6759283 (2004-07-01), Yasuda et al.
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patent: 2001-0112815 (2001-12-01), None
patent: 2001-112815 (2001-12-01), None
patent: 2003-0082144 (2003-10-01), None

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