Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2006-12-05
2006-12-05
Clark, S. V. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S781000, C438S614000
Reexamination Certificate
active
07145250
ABSTRACT:
An LSI package comprises an LSI element and a wiring board. The plurality of pin terminals of the LSI element each includes a first conductive layer and a second conductive layer superposed on the first conductive layer. The plurality of pin terminals of the wiring board each includes a third conductive layer joined to the second conductive layer, and the wiring board further comprises outer joining terminals. The first, second, and third conductive layers are made of materials causing the metallic bond between the second conductive layer and third conductive layer to be stronger than the metallic bond between the first conductive layer and second conductive layer. The LSI element is tested using the outer joining terminals of the wiring board. The second conductive layer and third conductive layer are joined to attain a metallic bond through aggregation derived from pressure, and are reliably brought into electrical contact with each other for a test. After the test is completed, the terminals of the LSI element are peeled off from the terminals of the wiring board. At this time, the second conductive layer is transferred to the third conductive layer, and the first conductive layer is left intact in each of the terminals of the LSI element. The LSI element is then mounted on another wiring board.
REFERENCES:
patent: 4930001 (1990-05-01), Williams
patent: 5367195 (1994-11-01), DiGiacomo et al.
patent: 5844320 (1998-12-01), Ono et al.
patent: 6249051 (2001-06-01), Chang et al.
patent: 6483195 (2002-11-01), Aoki et al.
patent: 6917118 (2005-07-01), Omori et al.
patent: 6972495 (2005-12-01), Fjelstad
patent: 2005/0098883 (2005-05-01), Hanke
patent: 2005/0110161 (2005-05-01), Naito et al.
patent: 2006/0060981 (2006-03-01), Paulus
patent: 5-190599 (1993-07-01), None
patent: 9-8442 (1997-01-01), None
patent: 10-335375 (1998-12-01), None
patent: 11-64389 (1999-03-01), None
patent: 2000-39452 (2000-02-01), None
patent: 2001-56347 (2001-02-01), None
patent: 2001-237277 (2001-08-01), None
Maruyama Shigeyuki
Nishino Toru
Tashiro Kazuhiro
Clark S. V.
Westerman, Hattori, Daniels & Adrian , LLP.
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