Method and apparatus for allocating entries in a branch...

Electrical computers and digital processing systems: processing – Processing control – Branching

Reexamination Certificate

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C712S237000

Reexamination Certificate

active

07096348

ABSTRACT:
A method (200) and apparatus (100) for allocating entries in a branch target buffer (BTB) (144) in a pipelined data processing system includes: sequentially fetching instructions; determining that one of the instructions is a branch instruction (210, 215, 220); decoding the branch instruction to determine a branch target address; determining if the branch target address can be obtained without causing a stall condition in the pipelined data processing system; and selectively allocating an entry of the BTB (144) based on the determination. In one embodiment, an entry of the BTB (144) is allocated if the branch instruction is not loaded into a predetermined slot (S1) of a prefetch buffer (102) and no other stall condition will occur. The method (200) and apparatus (100) combine the advantages of using a BTB (144) and branch lookahead to reduce stall conditions in the data processing system.

REFERENCES:
patent: 5701448 (1997-12-01), White
patent: 5835754 (1998-11-01), Nakanishi
patent: 5909566 (1999-06-01), Cai et al.
patent: 5996071 (1999-11-01), White
patent: 6154833 (2000-11-01), Murty
patent: 6157988 (2000-12-01), Dowling
patent: 6157998 (2000-12-01), Rupley et al.
patent: 6308322 (2001-10-01), Serocki et al.
patent: 6477640 (2002-11-01), Rupley, II et al.
PCT/US04/37627—International Search Report.

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