Method and apparatus for timing characterization of...

Details Method and apparatus for timing characterization of... Method and apparatus for timing characterization of...

2006-11-28

2006-11-28

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07143378

ABSTRACT:
Method and apparatus for forming timing parameters for a circuit design having a predefined routing topology within an integrated circuit is described. Sets of timing attributes are determined for the routing topology, each set of timing attributes being associated with one of a plurality of locations within the integrated circuit in which the circuit design may be placed. Timing parameters are formed in response to the sets of timing attributes. The timing parameters are then associated with the routing topology.

REFERENCES:
patent: 5659484 (1997-08-01), Bennett et al.
patent: 6701507 (2004-03-01), Srinivasan
patent: 6766504 (2004-07-01), Rahut et al.
patent: 2004/0196081 (2004-10-01), Srinivasan et al.

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